Pacher L, Paterno A, Monteil E, Demaria N, Panati S, Wheadon R , Ciciriello F, Marzocca C, De Robertis G, Loddo F, Licciulli F, Stabile A, Mattiazzo S, De Canio F, Gaioni L, Re V, Traversi G, Ratti L, Magazzu G, Marconi S, Placidi P, Della Casa G, Mazza G, Rivetti A, Da Rocha Rolo M, Rotondo F
Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC
Paterno A, Monteil E, Pacher L, Demaria N, Panati S, Wheadon R , Ciciriello F, Marzocca C, De Robertis G, Loddo F, Licciulli F, Stabile A, Mattiazzo S, De Canio F, Gaioni L, Re V, Traversi G, Ratti L, Magazzu G, Marconi S, Placidi P, Della Casa G, Mazza G, Rivetti A, Da Rocha Rolo M
A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC
Pacher L, Paterno A, Monteil E, Demaria N, Panati S, Wheadon R , Ciciriello F, Marzocca C, De Robertis G, Loddo F, Licciulli F, Stabile A, Mattiazzo S, De Canio F, Gaioni L, Re V, Traversi G, Ratti L, Magazzu G, Marconi S, Placidi P, Della Casa G, Mazza G, Rivetti A, Da Rocha Rolo M, Rotondo F
A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC
Panati S, Pacher L, Paterno A, Monteil E, Demaria N, Wheadon R , Ciciriello F, Marzocca C, De Robertis G, Loddo F, Licciulli F, Stabile A, Mattiazzo S, De Canio F, Gaioni L, Re V, Traversi G, Ratti L, Magazzu G, Marconi S, Placidi P, Della Casa G, Mazza G, Rivetti A, Da Rocha Rolo M, Rotondo F
First measurements of a prototype of a new generation pixel readout ASIC in 65 nm CMOS for extreme rate HEP detectors at HL-LHC
Proceedings, 2016 IEEE Nuclear Science Symposium and
Medical Imaging Conference: NSS/MIC 2016: Strasbourg,
France
Monteil E, Pacher L, Demaria N, Panati S, Wheadon R , Ciciriello F, Marzocca C, De Robertis G, Loddo F, Licciulli F, Stabile A, Mattiazzo S, De Canio F, Gaioni L, Re V, Traversi G, Ratti L, Magazzu G, Marconi S, Placidi P, Della Casa G, Mazza G, Rivetti A, Da Rocha Rolo M, Paterno A;
A prototype of a new generation readout ASIC in 65nm CMOS for pixel detectors at HL-LHC
Pacher, Luca and Monteil, Ennio and Rivetti, Angelo and
Demaria, Natale and Da Rocha Rolo, Manuel
A low-power low-noise synchronous pixel front-end chain
in 65 nm CMOS technology with local fast ToT encoding and
autozeroing for extreme rate and radiation at HL-LHC
Proceedings, 2015 IEEE Nuclear Science Symposium and
Medical Imaging Conference (NSS/MIC 2015): San Diego,
California, United States
Robertis, G. De and Loddo, F. and Mattiazzo, S. and Pacher, L. and Pantano, D. and Tamma, C
Design of a 10-bit segmented current-steering digital-to-analog converter in CMOS 65 nm technology for the bias of new generation readout chips in high radiation environment
S. Marconi, E.Conti, P. Placidi, A.Scorzoni, Jorgen Christiansen, Tomasz Hemperek
A SystemVerilog-UVM Methodology for the Design, Simulation and Verification of Complex Readout Chips in High Energy Physics Applications
Applications in Electronics Pervading Industry, Environment and Society pp 35-41 (2017)
Volume 409 of the book series Lecture Notes in Electrical Engineering (LNEE)
