RESEARCH PROGRAM

Pixel detectors at HL-LHC experiments will be exposed to unprecedented level of radiation and particle flux. CHIPIX65 project goal is the development of an innovative pixel chip using a CMOS 65nm technology for the first time in HEP community, for experiments with extreme particle rates and radiation at future High Energy Physics colliders. The CHIPIX65 project counts 35 members experts on the field, of which 20 are actual IC designers, constituting a substantial fraction of INFN expertise on microelectronics. The project is serving also the purpose of pushing the use of CMOS 65nm in the INFN across a wide community spread across several INFN groups. CHIPIX65 is organized in different Working Package: CHIPIX65 project is contributing to most of the research lines needed for the new pixel chip. For the study of the radiation qualification of the technology, the involvement of Padova group is fundamental for the study of Total Dose (TID), Total Displacement Damage (TDD), Single Event Effects using respectively X-ray, low energy protons and heavy ions coming from, in order, the X-ray machine at Padova INFN, the Legnaro INFN facilities of SIRAD at the Tandem and the CN accelerator. The analog very front end chain (preamplifier, discriminator, signal processing) is developed by the Torino, Bergamo and Pavia groups that are studying different architectures for synchronous and asynchronous front-ends, with very fast peak time and low noise solutions, and are foreseeing different Time-over-Threshold measurement methods. The design of several IPblocks are foreseen by CHIPIX65 like DAC and ADC (Bari), BandGap (Pavia), sLVDS-to-CMOS and CMOS-to-sLVDS transceivers (Pavia, Pisa, Torino), rad-hard by design memories like Dice SRAM and logic (Milano), High Speed Serializer/Deserialiser (Pisa) and others like PLL are under discussion. Under the study and definition of the digital architectural Perugia is mainly involved using high-level modeling tools (SystemVerilog) in order to collect sufficient statistic on the actual performance of the system in very high rate high energy physics experiments. The study of Input protocols to receive clock and trigger signals and commands to the chip is done by Pisa looking to data protection from SEU events using Hamming encoding or other options, while Bari is interested to provide monitoring data from the chip. In the year 2014, the CHIPIX65 project has designed the first CMOS 65nm design of prototypes for the first IP blocks and for the first small matrixes of pixels dedicated to the study analog very front end architectures. The prototypes have been submitted in October 2014 as three different dices of 2x2 mm2 to the foundry and are now under test in the different groups. The CHIPIX65 is part of the international RD53 collaboration. RD53 Collaboration is a recognised experiment with 20 institutes from nine different countries (Czech Republic, France, Germany, Italy, Netherland, Spain, Switzerland, UK, USA) and about 120 member with a large presence of chip designers. The collaboration has the support of both ATLAS and CMS and is almost equally composed by people from the two experiments. By internal constitution, a Memorandum of Understanding signed by all institutes, there are two cospokespersons one member of ATLAS and the other of CMS, a Collaboration and a Management Boards. There are six working groups: radiation qualification, top level design, simulation test bench, I/O, analog design, IP-block.

Evolution of requirements along HEP pixel detectors

  • Table with main requirements for current, phase-1 LHC and future HL_LHC pixel detector