WORKING PACKAGES
WP1: Radiation Hardness
Aim of the CHIPX65 proposal is focused on the design of a hybrid pixel read-out chip for the rate and
radiation expected in the ATLAS and CMS Phase 2 upgrades. In particular the chip must work reliably in an
unprecedented radiation environment of 10 MGy Total Ionizing Dose (TID) and 10e16 n.eq./cm2 in 10 years.
Acquired pixel information must be processed and stored reliably in such hostile radiation environment.
A dedicated effort is needed to investigate such high radiation tolerance and this will be a central concern of the
project.
The chosen CMS 65nm technology has shown to be more radiation hard than 130nm, but it has been tested
only up to 3 MGy. Moreover, the role of time delivery of the total dose and possible annealing effects should
be understood, together with a temperature dependency. The program of the characterization of the radiation
hardness of this novel technology has to be continued further for understanding its use in the front end of pixel
detectors, and it is the purpose of WP1 of CHIPIX65 program.
Characterization is not limited to single transistors but covers the whole logic cell library. One can expect
several digital storage elements (e.g. pixel data, configuration data, state machines) on the chip will have its
content corrupted by radiation induced Single Event Upsets (SEU) every second.
Modified transistor simulation models must be extracted to allow the degradation to be taken into account
during the design phase. This might require the creation of a full custom logic cell library.
On the contrary CMOS transistors are normally very resistant to Total Displacement Damage (TDD) but this
has never be verified at this huge fluence values. Bipolar devices used in certain basic reference blocks will
most likely become so affected that alternative circuits have to be developed.
Characterization of the technology at the required radiation levels is of fundamental importance for the
experiment. The following measurements will be done:
-
1.TID effects on test structures and then on transistors at standard, reference, X-ray machine. Dependence of
the damage from dose rate will be studied along with the presence of annealing effects and their dependence
from temperature. In addition, to reduce the long irradiation times needed at the X-ray machines to attain 10
MGy, alternative radiation sources, as low energy electron linacs, will be investigated.
- 2. TDD effects by exposing test structures to proton and neutron beams. TID and TDD interplay will be
analyzed also by comparing results from different subsequent irradiations with X-rays and neutrons.
- 3. Sensitivity to SEE, in particular to SEU (Single Event Upsets) and SET (Single Event transient), of logic
cells with ion beams.
The technology characterization to TID and TDD will start immediately using test structures already available
at CERN. Characterization of transistors developed within the Collaboration will follow, as soon they will
become available.
Sensitivity to SEE of logic cell arrays will be performer in the second year and and will extend in the first part of
the third year. Measurements could include micro-mapping of the sensitivity.
WP2: Digital Electronics
Fault tolerant chip architectures will be explored, developed and simulated
using the HDVL (Hardware
Description and Verification Language)
System Verilog at both architectural level and logic level.
Such tool,widely adopted for complex designs in industry, will be used for creating a dynamic and reusable verification
and simulation environment. The performance of alternative pixel readout chip architectures will therefore be
analyzed at increasingly refined level as the design progresses. Architectures will be gradually optimized for
minimal power consumption and very compact layout area to accommodate required digital signal processing
and buffering functions.
In order to do this they will feature group of pixels (i.e. pixel regions) that share
buffering logic; one critical aspect of such strategy
is the number of pixels to put in a single pixel region and
the communication between them.
Independently of the actual pixel chip architecture implementation and optimization, a number of vital generic
functions are required for a complete ASIC system. Despite that such functions (generally called IP blocks)
are relatively common functions found in modern commercial integrated circuits, they have to be designed
and optimized specifically for the pixel application because
of the very hostile radiation environment with
significant TID effects on the basic transistors and radiation induced single event upsets. Together they
represent a large design effort, but one that
ideally lends itself to be shared
among collaborating gro
ups.
Typically each of these blocks will be designed
by a single designer or team at a single institute
WP3: Analog Electronics
Different low noise and low power analog
circuit architectures and implementations will be developed for the
critical amplification of the
small pixel signals followed by appropriate signal shaping. Very low power
digitization schemes based on time over threshold
(ToT) and successive approximation ADCs will be evaluated and one of them will be implemented and optimized for massively
parallel use in a large pixel chip. Biasing circuits, charge sensitive
amplifiers, discriminators, clock regeneration circuits; will be
designed for use in very high level radiation
environments. Circuits for fast readout and high-resolution time measurements
for high rate pixel detectors
like Phase Locked Loops (PLL) and timing measu
rement circuits will be
developed. All developed circuits will be implemented and prototyped in
MPW runs of a 65nm CMOS technology and
extensively characterized from the standpoint of
a
nalog
p
erformance and of
radiation effects
WP4: Chip Integration
This Work Package will take care of the global design of the pixel readout chip, from the definition of the
architecture and floorplan, to the implementation of a common environm
ent for simulation and verification.
The activity of WP4 is even more crucial in the case of a 65 nm CMOS integrated circuit than it already was
for previous chip generations in former technology nodes. The greater complexity of design tools, along with
the increased integration density, foster the need of tackling many issues at a global system level, taking into
account that low-noise, high-accuracy analog blocks will be merged into a mostly digital environment.
In a first stage of the work, WP4:
- will cooperate with the other WPs and with other RD53 groups to define requirements and
specifications of the readout chip. On the basis of these specs, WP4 will collaborate to the study of
the architecture for the data readout of the pixel matrix. This preliminar
y stage will be essential to understand how some critical parameters should be kept under control in the global chip design, to
avoid a degradation of the performance of analog and digital cells.
-
will take care of the definition of a common CAD platform a
nd standard formats for design
information exchange, and will coordinate the definition of design guidelines for power grid, clock
tree, and signal interfaces between different blocks (e.g., for hard blocks: LEF files for geometry;
Liberty files for timing
/power). Pad rings structure, use of standard cells provided by the foundry,
and number of routing levels shall be defined at the beginning of the project.
In a second stage of the project, WP4 will provide an analysis of design solutions to the diverse is
sues that are
crucial for the correct operation of the chip. These are just some of the problems that WP4 will tackle:
-
Since the power dissipation of the chip will have to be kept under control even considering the huge
amount of digital data flow, we will
study possible techniques for distributing clock signals to the
pixels and for transmitting and receiving data on- and off-chip in a low-power fashion. This may
involve the use of non-standard digital levels and the consequent need for appropr
iate regeneration circuits.
-
Distributing power supplies to a large pixel matrix may be critical, since even small voltage drops
along power lines may affect the performance of analog circuits and cause a non-uniform behavior of
pixel readout cells in different matrix regions. Techniques for the mitigation and compensation of
power supply drops will be devised and implemented by WP4 in the global chip design. On-chip
power conditioning and regulation is also crucial, and WP4 will study the performance of voltage
regulators and DC-DC converters that are being developed by the community working on 65 nm CMOS.
-
Digital-to-analog interferences might impair the detection of small signals in analog cells and induce
fake hits. WP4 will define the best design strategy to prevent
these effects to occur in a unacceptable way.
- The chip will contain a complex analog and digital system that needs to be monitored and calibrated
in an accurate way. WP4 will study the integration in the chip of temperature monitoring ADCs,
voltage calibra
tion DACs, circuits for the injection of analog test signals in the pixel cells, PLLs for
the regeneration of external clock signals, and so on. Some of these blocks may be developed by the
community that is starting to create a common library of IP blocks
in the 65 nm technology. WP4 will
monitor these developments and contribute to them when this will be needed for the design of the
pixel readout chip
